CS2CA17NU-Computer Architecture and Networking

Module Provider: Computer Science
Number of credits: 20 [10 ECTS credits]
Level:5
Semesters in which taught: Semester 1 / 2 module
Pre-requisites: CS1PC20NU Programming in C/C++ and CS1FC16NU Fundamentals of Computer Science
Non-modular pre-requisites:
Co-requisites:
Modules excluded:
Current from: 2022/3

Module Convenor: Dr Hong Wei
Email: h.wei@reading.ac.uk

Type of module:

Summary module description:

This module introduces Computer Architecture, based on RISC/MIPS architecture, in the autumn term and Computer Networking in the spring term.

The Module leads at NUIST is TBD.

Aims:

The module consists of two parts. The first part, Computer Architecture, provides students fundamental knowledge of modern computer architectures in terms of instruction set architecture, organisation and hardware; and the second part, Computer Networking introduces the theories underlying computer communications and show how these are applied in real world network applications.

This module also encourages students to develop a set of professional skills, such as problem solving, organisation and time management, creativity, numeracy, end-user awareness, and self-reflection.

Assessable learning outcomes:

Students who complete this module will have:

• basic skills for computer architecture design;


• ability to quantitatively evaluate computer performance by using benchmark suites;


• skills to improve computer performance by using hardware and software techniques;


• core concepts and knowledge of network architecture and communication protocols;


• ability to implement the concepts in real world network applications.

Additional outcomes:

ARM (RISC processor) assembly programming skills and insight of MIPS architecture can be obtained from laboratory practicals; programming skills are built into coursework assignments.

Outline content:

The module introduces the underlying theory of modern computer architecture in terms of instruction set architecture, organisation, and hardware. It begins with an introduction to the fundamentals of computer design for Von Neumann architecture, and continues with an examination of the components of processor, memory and input/output. DLX, which is an educational edition of MIPS and RISC architecture, is used as a model machine in teaching. An important theme is the relationship between architecture and performance. The module covers modern techniques for improving computer performance, such as instruction-level parallel processing (pipelining), and cache-memory-hierarchy design. The role of Input/Output in computer architecture with storage systems is also examined from the design point of view.

The core concepts of network architecture and communication protocols, which present in the framework of multi-tier architectures, are discussed in the spring term. These include Local Area Networking (LAN) routing and Ethernet protocols; Internetworking; and error, congestion and flow control. The module covers network technologies ranging from local area networks to the Internet, including EthernetÌýwith a focus on TCP/IP, IP addressing, routing protocols, and congestion control schemes within the Internet. An introduction is also given to the core Internet applications, such as email, web serving and name resolution.

Brief description of teaching and learning methods:

Lectures supported by laboratory practicals and a number of assignments.

Contact hours:

Ìý	Semester 1	Semester 2
Lectures	16	12
Practicals classes and workshops	8	8
Guided independent study:	Ìý	Ìý
Ìý Ìý Wider reading (independent)	10	12
Ìý Ìý Exam revision/preparation	20	20
Ìý Ìý Advance preparation for classes	10	10
Ìý Ìý Preparation for tutorials	13	17
Ìý Ìý Preparation of practical report	10	20
Ìý Ìý Revision and preparation	10
Ìý Ìý Reflection	2	2
Ìý	Ìý	Ìý
Total hours by term	99	101
Ìý	Ìý	Ìý
Total hours for module	200

Summative Assessment Methods:

Method	Percentage
Written exam	70
Set exercise	30

Summative assessment- Examinations:

One 3-hour examination paper in May/June.

Summative assessment- Coursework and in-class tests:

Two on-line tests (each 7.5%) for computer architecture, and one lab-based coursework (15%) for computer networking.

Formative assessment methods:

Penalties for late submission:

The Support Centres will apply the following penalties for work submitted late:

• where the piece of work is submitted after the original deadline (or any formally agreed extension to the deadline): 10% of the total marks available for that piece of work will be deducted from the mark for each working day (or part thereof) following the deadline up to a total of five working days;
• where the piece of work is submitted more than five working days after the original deadline (or any formally agreed extension to the deadline): a mark of zero will be recorded.

The University policy statement on penalties for late submission can be found at: /cqsd/-/media/project/functions/cqsd/documents/cqsd-old-site-documents/penaltiesforlatesubmission.pdf
You are strongly advised to ensure that coursework is submitted by the relevant deadline. You should note that it is advisable to submit work in an unfinished state rather than to fail to submit any work.

Assessment requirements for a pass:

A mark of 40% overall.

Reassessment arrangements:

One 3-hour examination paper in August/September. Note that the resit module mark, used to determine progression, will be the higher of (a) the mark from this resit exam and (b) an average of this resit exam mark and previous coursework marks, weighted as per the first attempt (70% exam, 30% coursework).

Additional Costs (specified where applicable):

Last updated: 22 September 2022